Input/Output Overload: Modern vehicles have over 90 smart sensors, 800 sensors and loads, requiring zonal MCUs to have denser ...

Winning the ECSO STARtup Award 2025 gives Xiphera increased visibility within the European cybersecurity ecosystem and opens doors for new collaborations and customer relationships.

As part of this initiative, Analogue Insight and Tetrivis have signed a Memorandum of Understanding (MoU) to jointly develop the chiplet, aligning their IP roadmaps, technology resources, and customer ...

Expedera launches its Origin Evolution NPU IP, bringing hardware acceleration to meet the computational demands of running ...

Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports ...

A Paradigm Shift in eFPGA Customization. Advancing Programmability in the Next Generation of SoCs . In an era of continual ...

In a landscape defined by AI acceleration , chiplet-based system integration, and upcoming post-quantum challenges, Secure-IC ...

SINGAPORE -- May, 20 2025 – GlobalFoundries (Nasdaq: GFS) (GF) today announced plans to expand its capabilities in advanced packaging through a new Memorandum of Understanding (MOU) signed with the ...

The ENS92051 is the dual-beam Ku-band receiver (Rx) supporting eight channels with separate amplitude and phase control. The Rx carrier frequency range is 10.7 to 12.75 GHz with an instantaneous ...

In fifteen years, RISC-V has gone from an academic project at UC Berkeley to one of the major technological trends in compute. The ISA has since flourished in an era that appreciates its royalty-free, ...

At around the same time, the open and configurable RISC-V instruction set architecture (ISA) is experiencing rapid adoption across diverse markets. This growth aligns with rising SoC complexity and ...

"Native Red Hat Enterprise Linux support on SiFive’s HiFive Premier P550 board offers developers a substantial enterprise-grade toolchain for RISC-V. This is a pivotal step forward in enabling a ...