What is a Latch-up? Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either ...
A technical paper titled “Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS” was just published by researchers at Anhui University, Hefei University of ...
Editor’s note: I am pleased to bring you an important technical blog by Fernando Lavalle, a Ph.D. student at Texas A&M University and his colleague, Suraj Prakash, who have been working and studying ...
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